Phase lock loop circuits have been used in various electronic circuits. Here, a description will be given on a phase lock loop circuit which is used in the destuffing section of a PCM multiplexing/separating apparatus.
There is a stuffing synchronization system as a method for multiplexing data of multiple channels which are asynchronous. In this system, an extra pulse is inserted (stuffed) as needed into asynchronous data to increase the data speed before a multiplex operation and the channels are given a pseudo synchronous relation, and then the data is multiplexed to be transferred. A data-receiving side divides the multiplexed data channel by channel, and eliminates (destuffs) the extra pulse that a data-sending side has inserted to reproduce the original data. Since the reproduced data has data absent empty space from which the extra pulse has been removed, time dependent fluctuation (jitter) will occur in the flow of data. A jitter suppressor having a phase lock loop circuit is therefore provided in the destuffing section of the multiplexing/separating apparatus.
FIG. 1 exemplifies a destuffing section in a conventional multiplexing/separating apparatus.
Reference numeral "10" denotes a frequency divider which frequency-divides a received clock CKL. The frequency divider 10 starts frequency division when receiving an enable pulse ENA. The frequency-divided output is used as write address data for a memory 20 to store input data Din. The output of the most significant bit of the frequency divider 10 is sent to one of the input portions of a phase comparator 30.
The phase comparator 30 has the other input portion supplied with the output of the least significant bit of the frequency-divided output of a frequency divider 40, like the frequency divider 10. The frequency divider 40 frequency-divides the output from a voltage controlled oscillator (VCO) 70. The output of the frequency divider 40 is used as read address data for the memory 20.
Phase difference data from the phase comparator 30 is supplied to a low-pass filter (LPF) 50 to be smoothed, and after being amplified by an amplifier 60, it is then sent to the control terminal of the voltage controlled oscillator 70 to control an oscillation frequency.
The enable pulse ENA is sent from a timing generator (not shown) in the multiplexing/separating apparatus, in correspondence to valid data which is the received data excluding a frame sync pulse, a stuffing pulse, etc. The memory 20 is a dual port memory which can designate the write and read addresses, independently. The memory 20, like the frequency divider 10, is controlled in accordance with the enable pulse ENA, and only valid data in the received data is to be intermittently written in the memory 20.
In this destuffing section, the oscillation frequency from the voltage controlled oscillator 70 is so controlled as to provide the steady average of the phase differences between the write and read addresses of the memory 20. The data intermittently written in the memory 20 is read out through buffering as sequential data Dout which has an equal average speed, thereby suppressing the jitter.
The phase locked loop of the above-described destuffing section includes the phase comparator 30 of a digital type since phase comparison inputs are digital signals. The phase comparator 30 of a digital type can be easily realized by an exclusive-OR circuit, a set/reset flip-flop circuit, etc. Since the phase comparison output includes analog information for controlling the frequency from the voltage controlled oscillator 70, however, it is necessary to stabilize the amplitude of a fanout with resect to changes in temperature and voltage. In other words, a change in the amplitude of the fanout from the phase comparator varies the phase difference between the write and read addresses of the memory 20. Such a phase change is called a steady phase difference. Increasing that difference induces the overflow or underflow of the memory 20 and causes an error in data which is read out from the memory 20. The change in the amplitude of the fanout from the phase comparator also varies the central value of an oscillation frequency from the voltage controlled oscillator, and equivalently narrows the lock range of the phase locked loop. Some countermeasures should be taken to prevent these shortcomings. To prevent an increase in the steady phase difference and narrowing of the lock range, the gain of the amplifier 60 is raised to increase the loop gain of the phase locked loop. The increase in the loop gain however results in more jitters in reproduced clocks.
To stabilize the amplitude of the fanout of the phase comparator, therefore, the following measures have conventionally been taken: stabilizing the source voltage of the phase comparator by a local regulator, and constituting the phase comparator by logic elements showing a slight change in temperature.
FIG. 2 exemplifies the structure of an output stabilizer in the conventional phase comparator.
The outputs from the frequency dividers 10 and 40 are sent respectively to logic level converters 31 and 32 which convert a CMOS level (+0.3 to +4.4 V) into an emitter coupled logic (ECL) level (-1.6 to -1.0 V). The outputs of the logic level converters 31 and 32 are supplied to the phase comparator 30 constituted by an exclusive-OR circuit. Reference numeral "33" denotes a source IC (local regulator), which has a source output terminal grounded via a bypass capacitor 35 and supplies the source output to the phase comparator 30. The source output terminal is also connected to the output terminal of the phase comparator 30 through an emitter resistor (the emitter resistor of the ECL exclusive-OR circuit)
In this arrangement, the source voltage of the ECL exclusive-OR circuit is to be stabilized by the source IC 33.
If the phase comparator is constituted by the ECL exclusive-OR circuit, the fluctuation of the output amplitude is compensated for by the IC (e.g. ECL 100K series), and this phase comparator significantly improves a change in output level compared with a phase comparator constituted by a CMOS exclusive-OR circuit. The phase comparator, if designed to have a CMOS logical circuit structure, is considered equivalent to a complementary switch which opens and closes a power supply side and a ground (GND) side. A change in the inner resistance of the switch due to a change in the source voltage or a temperature change is likely to appear directly as a change in amplitude of the fanout.
The above-described phase comparator which has an ability to compensate for an output amplitude however requires the level conversion, thus complicating the circuit. Power consumption is increased because that phase comparator uses the ECL as a logic element. The phase comparator above is not therefore suitable in the case of integrating (gate-arraying) the destuffing section for its miniaturization and lower power consumption.
As explained above, in the conventional phase lock loop circuit, an oscillation frequency control voltage from the voltage controlled oscillator is influenced by a voltage or temperature change on a control voltage producing side, so the change in control voltage causes a phase difference between an input signal and an oscillation output. The above influence gives rise to a serious problem, particularly for the destuffing section in the multiplexing/separating apparatus, for which it is difficult to set a large loop gain in order to reduce the jitter in the reproduced clock. The use of a phase comparator with an ECL structure which can stabilize the fanout amplitude en route of the phase locked loop complicates the circuit structure, and is inadequate to decrease power consumption.
It is therefore an object of the present invention to provide a phase lock loop circuit with low power consumption and a simple structure, which can stabilize the output of a phase comparator, and can provide a phase-locked signal that follows up an input signal at high accuracy.